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CME-M7(Hua Mountain)Series


Highlights:




Introduction:

 

The CME-M7 is an intelligent true system on a chip, integrating the ARM Cortex™-M3 32-bit RISC core, high performance FPGA and plenty of peripherals. The high-performance ARM Cortex™-M3 32-bit RISC core can operate at up to 300 MHz, and with memory protection unit(MPU) and high-speed embedded memoriesCME delivers the much anticipated single chip solution. CME’s M7 family of FPGAs are the lowest cost, targeted to high-volume, cost-sensitive applications, enabling you to meet increasing market requirements.

 

CME-M7 Densities range from 7K to 12K LUTs(Look Up Table), Optimized FPGA and ARM interfaces, Improved system performance through a hard core processor system (cortex-m3) for FPGA bandwidth interconnect, hardware acceleration, and increased memory performance. Specially, Memory is separated between the P-region and the D-region for the ARM core to run instruction code and data code.

 

CME M7 can be widely used in video display, industrial control, information security, telcomunication, video surveillance, medical equipment, instrument, automation, appliance etc..

 


Device features:



  • --Up to 12K LUTs
  • --Rich I/Os
  • --Memory Up to 648K bits
  • --DSP Up to 48 18 x 18 multipliers or 96 12X9 multipliers
  • --8 external input clocks, 1 external crystal clock input
  • --4 PLLs support frequency multiplication, frequency division, phase-shifting, de-skew 
  • --Multi-voltage, multi-standard, multi-banks I/O
  • -        3.3V to 1.5V single-ended and differential I/O standards and protocols
  • -        Low-cost HSTL and SSTL memory interfaces
  • -        Dedicated Serdes Circuit for LVDS, DDR II/III standard
  • -        Up to 800 Mbps data transfer rate per differential I/O
  • -        Programmable driving strength
  • -        Programmable slew rate
  • -        programmable input and output delay
  • -        Calibrated series and parallel termination resistor



MSS:


ARM® Cortex™-M3 processor


  •         300 MHz maximum frequency, 1.25 DMIPS/MHz performance at 0 wait state memory access
  •         Single-cycle multiplication and hardware division
  •         JTAG interfaces
  •         Cortex-M3 Embedded Trace Macrocell™
  •         Sleep, Deepsleep low power mode



Memories:


  •         128 KB Instruction Code SRAM
  •         64 KB Data SRAM
  •         8KB Instruction Code cache



Peripheral:


  •         High-performance hard DDRII/III controller support 16bit DDRII/III memory up to 333MHz
  •         USB High Speed OTG 2.0 & PHY
  •         10/100/1000Mbps Ethernet MAC
  •         8 channels DMA
  •         2 I2C
  •         2 SPI
  •         3 UAR
  •         4 32 bit Timer
  •         1x32 GPIO
  •         2  CAN 2.0A/B
  •         Low-power RTC
  •         Dual 12 bit 1MSPS ADC



Configuration:


  •         JTAG Mode
  •         AS Mode
  •         PS Mode



Security:


  •         Encrypted bitstream with 256-bit AES
  •         Based Efuse and SPI Flash security settings
  •         Protection against copying, overbuilding, cloning and tampering with both of the FPGA and M3 processor firmware


Documents:


Datasheet





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