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Intellectual Property 



CME provides commonly used Intellectual Property (IP) building blocks that are specifically targeted and optimized to run on CMEs FPGA fabric. These IP blocks are easy to use and can be easily integrated into any design through Primace design tools.


We are continually improving and incrementing our IP portfolio, and if there is a specific IP that is not in our list, please contact us.





Type Name  Description Resources Devices  Provider
Demo Doc
Interface Protocol  CAN2.0 The CAN2.0 IP controller implements the BOSCH CAN message transfer protocols 2.0A and 2.0B.
Specification 2.0A (which is equivalent to CAN 1.2) covers standard message formats (11-bit identifier);
Specification 2.0B covers both standard and extended message formats (both 11-bit and 29-bit identifiers).
CAN_example_M5 CAN2.0 user
guide(EN01) 
CME-M5  CME 
 USB2.0 This IP Core provides a function (peripheral device) interface.  It can be used to interface almost any peripheral to a computer via USB. This core fully complies to the USB 2.0 specification and can operate at USB Full and High Speed rates. USB2.0_example_
M5&M7  
USB2.0 user 
guide(EN02)
CME-M5 CME-M7  CME
 Ethernet MAC This IP fully integrated 10/100M Ethernet MAC and with full-duplex/half-duplex operation.It  supports DPRAM for frame transmission and reception which work in Ping-Pong mode. Ethernet_MAC_
example_M5&M7 
 
Ethernet MAC 
user guide(EN02)

CME-M5 CME-M7 
 CME
 UART The IP provides a simplified interface connected to EMIF bus of 8051 core in CME FPGA, and it is a full-duplex serial communication interface (80C51 like).
UART_example
_M5&M7
    
UART user
guide(EN03)
CME-M5 CME-M7 CME-HR3  CME
 I2C This External I2C IP basically has the same behavior like 8051's internal I2C. The IP provides the interface to EMIF (External Memory Interface) of 8051 core in CME FPGA and can be programmed to work as master or as slave.
 I2C_example_M5  I2C user
guide(EN01)
CME-M5 CME-HR3    CME
 SPI Controller This External SPI IP basically has the same behavior like 8051's internal SPI controller. The IP provides the interface to EMIF (External Memory Interface) of 8051 core in CME FPGA and can be programmed to work as master or as slave device. SPI_Controller_
example_M5
SPI Controller
user 
guide(EN02)
CME-M5 CME-HR3  CME
AHB2APB Bridge The IP works as AHB bus slave and APB bus master.The APB slaves blocks can be connected to AHB bus if there is no APB bus provided. AHB2APB_
Bridge_example_M7
AHB2APB
Bridge user
guide(EN01)
CME-M7 CME
LVDS The IP provides both Transmitter(serializer) and Receiver(deserializer). LVDS_example_HR3 LVDS_user_
guide(EN01)
CME_HR3 CME
PCI The PCI Target IP provides a function PCI(peripheral component interconnect)interface. PCI_example PCI_user_
guide(EN01)
CME_M5 CME_M7 CME
Memory Interface SDR SDRAM Controller This IP provides a simplified interface to industry standard SDR SDRAM. The SDR SDRAM Controller is available in Verilog HDL and optimized for the CME-M5 architecture. SDR_SDRAM_
Controller_
example_M5
SDR-SDRAM
Controller
user 
guide(EN01)
CME-M5 CME-HR3   
 CME
AHB interface EMB The EMB IP has two types of interface: memory interface and AHB interface.Users can choose the interface and access the memory AHB_interface
_EMB _
example_M7
  
AHB
interface
EMB user 
guide(EN01)
CME-M7 CME
FIFO/AHB interface   The FIFO IP has two types of interface: memory interface and AHB interface which can be configured by users.It supports asynchronous FIFO and synchronous FIFO . AHB_
interface
_FIFO_
example_M7 
FIFO user
guide(EN11)

AHB 
interface FIFO 
user 
guide(EN11)
CME-M5 CME-M7 CME-HR3 CME
FPGA features and debugging Debugware The Debugware is an embedded logic analyzer. Designer always wants to inspect the signal transition inside an FPGA.
The Debugware uses the embedded memory to store the internal signals waveform, and retrieves data via JTAG port after trigging events happened.
  CME-M5 CME-M7 CME-HR3  CME
DSP ECC  The IP provides Single Error Correction - Double Error Detection (SECDED) capability. The ECC IP is available in Verilog HDL and optimized for the CME-M5 architecture. ECC_example_M5 ECC user 
guide(EN01)
CME-M5
CME-HR3
 CME
Extended MAC  The extended MAC IP is developed from the CME-M5 device MAC, make the CME-M5 more flexible when used in digital signal  processing (DSP).        Extended_MAC
_example_M5
Extended
MAC user
guide(EN02)
CME-M5  CME
Floating_Point The IP supports single precision floating point 6 kinds of functions and cmpliance with IEEE-754 standard. Floating_Point
_example_
M5&M7
    
Floating_
Point_
user_
guide(EN01)
CME-M5 CME-M7 CME